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20 v, 4 a, synchronous, step-down dc-to-dc regulator data sheet adp2384 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features input voltage: 4.5 v to 20 v integrated mosfet: 44 m/11.6 m reference voltage: 0.6 v 1% continuous output current: 4 a programmable switching frequency: 200 khz to 1.4 mhz synchronizes to external cl ock: 200 khz to 1.4 mhz 180 out-of-phase clock synchronization precision enable and power good external compensation internal soft start with external adjustable option startup into a precharged output supported by adisimpower design tool applications communications infrastructure networking and servers industrial and instrumentation healthcare and medical intermediate power rail conversion dc-to-dc point-of-load applications typical applications circuit adp2384 bst fb comp pgood gnd vreg rt sync ss l c vreg r t sw pgnd en pvin c in v in c bst c out v out r top r bot c c r c c ss 10725-001 figure 1. 100 50 55 60 65 70 75 80 85 90 95 0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 4.0 efficiency (%) output current (a) v out = 1.2v v out = 3.3v v out = 5v 10725-002 figure 2. efficiency vs. output current, v in = 12 v, f sw = 300 khz general description the adp2384 is a synchronous, step-down dc-to-dc regulator with an integrated 44 m, high-side power mosfet and an 11.6 m, synchronous rectifier mosfet to provide a high efficiency solution in a compact 4 mm 4 mm lfcsp package. this device uses a peak current mode, constant frequency pulse- width modulation (pwm) control scheme for excellent stability and transient response. the switching frequency of the adp2384 can be programmed from 200 khz to 1.4 mhz. to minimize system noise, the synchronization function allows the switching frequency to be synchronized to an external clock. the adp2384 requires minimal external components and operates from an input voltage of 4.5 v to 20 v. the output voltage can be adjusted from 0.6 v to 90% of the input voltage and delivers up to 4 a of continuous current. each ic draws less than 120 a current from the input source when it is disabled. this regulator targets high performance applications that require high efficiency and design flexibility. external compensation and an adjustable soft start function provide design flexibility. the power- good output and precision enable input provide simple and reliable power sequencing. other key features include undervoltage lockout (uvlo), overvoltage protection (ovp), overcurrent protection (ocp), short-circuit protection (scp), and thermal shutdown (tsd). the adp2384 operates over the ?40c to +125c junction temperature range and is available in a 24-lead, 4 mm 4 mm lfcsp package.
adp2384 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 a pplications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 11 theory of operation ...................................................................... 12 control scheme .......................................................................... 12 precision enable/shutdown ...................................................... 12 internal regulator (vreg) ....................................................... 12 bootstrap circuitry .................................................................... 12 oscillator ..................................................................................... 12 synchronization .......................................................................... 12 soft start ...................................................................................... 13 power good ................................................................................. 13 peak current - limit and short - circuit protection ................. 13 overvoltage protection (ovp) ................................................. 14 undervoltage lockout (uvlo) ............................................... 14 th ermal shutdown .................................................................... 14 applications information .............................................................. 15 input capacitor selection .......................................................... 15 output voltage setting .............................................................. 15 voltage conversion limitations ............................................... 15 inductor selection ...................................................................... 15 output capacitor selection ....................................................... 16 programming the input voltage uvlo .................................. 17 compensation design ............................................................... 17 adisimpower design tool ....................................................... 17 design example .............................................................................. 18 output voltage setting .............................................................. 18 frequency setting ....................................................................... 18 inductor selection ...................................................................... 18 output capacitor selec tion ....................................................... 19 compensation components ..................................................... 19 soft start time program ........................................................... 19 in put capacitor selection .......................................................... 19 recommended external components .................................... 20 circuit board layout recommendations ................................... 21 typical applications circuits ........................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 8/ 12 revision 0: initial version
data sheet adp2384 rev. 0 | page 3 of 24 specifications v pvin = 12 v, t j = ? 40 c to +125 c for minimum/maximum specifications, and t a = 25 c for typical specifications, unless otherwise noted. table 1. pa rameter symbol test conditions/comments min typ max unit pvin pvin voltage range v pvin 4.5 20 v quiescent current i q no s witching 2.1 2.9 3.6 ma shutdown current i shdn en = gnd 45 80 120 a pvin undervoltage lockout threshold uvlo p vin rising 4.3 4.5 v p vin falling 3.5 3.8 v fb fb regulation voltage v fb 0c < t j < 85c 0.594 0.6 0.606 v ?40 c < t j < 125c 0.591 0.6 0.609 v fb bias current i fb 0.01 0.1 a error amplifier (ea) transconductance g m 340 470 600 s ea source current i source 40 60 80 a ea sink current i sink 40 60 80 a internal regulator (vreg) vreg volt age v vreg v pvin = 12 v, i vreg = 50 ma 7.6 8 8.4 v dropout voltage v pvin = 12 v, i vreg = 50 ma 340 mv regulator current l imit 65 100 135 ma sw high - side on resistance 1 v bst ? v sw = 5 v 44 70 m? low - side on resistance 1 v vreg = 8 v 11.6 20 m? high - side peak current limit 4.8 6.1 7.4 a low - side negative current - limit threshold voltage 2 20 mv sw minimum on time t min_on 125 168 ns sw minimum off time t min_o ff 200 260 ns bst bootstrap voltage v b oot 4.5 5 5.5 v oscillator (rt pin) switching frequency f sw r t = 100 k ? 530 600 670 khz switching frequency range f sw 200 1400 khz sync synchronization range 2 0 0 1 4 0 0 k hz sync minimum pulse width 100 ns syn c minimum off time 100 ns sync input high voltage 1.3 v sync input low voltage 0.4 v ss internal soft start 1600 clock cycle s ss pin p ull - up current i ss_up 2.5 3.2 3.9 a pgood power - good range fb r ising t hreshold pgood from low to high 95 % fb rising hysteresis pgood from high to low 5 % fb f alling t hreshold pgood from low to high 105 % fb falling hysteresis pgood from high to low 11.7 %
adp2384 data sheet rev. 0 | page 4 of 24 pa rameter symbol test conditions/comments min typ max unit power - good deglitch time pgood from low to high 1024 clock cycle pgood from high to low 16 clock cycle power - good leakage current v pgood = 5 v 0.01 0.1 a p ower - good output low voltage i pgood = 1 ma 125 200 mv en en rising threshold 1.17 1.28 v en falling threshold 0.97 1.07 v en source current en v oltage below falling threshold 5 a en v oltage above rising threshold 1 a thermal shutdown thermal shutdown threshold 150 c thermal shutdown hysteresis 25 c 1 pin - to - pin measurement. 2 guaranteed by design.
data sheet adp2384 rev. 0 | page 5 of 24 absolute maximum rat ings table 2. parameter rating p vin, en, pgood ? 0.3 v to + 22 v sw ? 1 v to + 22 v bst v sw + 6 v fb , ss, c o m p, sync, rt ? 0.3 v to +6 v vreg ? 0.3 v to + 12 v pgnd to gnd ? 0.3 v to +0.3 v operating junction temperature range ? 40 c to +125c storage temperature r ange ? 65c to +150c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is , a device soldered in a 4 - l ayer, jedec s tandard circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit 24-l ead lfcsp _wq 42.6 c/w esd caution
adp2384 data sheet rev. 0 | page 6 of 24 pin configuration an d function d escriptions 2 1 3 4 5 6 18 17 16 15 14 13 sw sw gnd vreg fb com p pgnd 25 gnd 26 sw sw bst pvin pvin pvin notes 1. the exposed gnd pad must be soldered to a large, external, copper gnd plane to reduce thermal resistance. 2. the exposed sw pad must be connected to the sw pins of the adp2384 by using short, wide traces, or else soldered to a large, external, copper sw plane to reduce thermal resistance. 8 9 10 1 1 7 pgnd pgnd pgnd pgnd 12 pgnd sw 20 19 21 en pvin pgood 22 rt 23 sync 24 ss adp2384 t op view 10725-003 figure 3 . pin configuration table 4 . pin function descriptions pin o. nemonic description 1 comp error amplifier o utput. connect an rc network from comp to gnd. 2 fb feedback voltage sense i nput. connect to a resistor divider from the output voltage, v out . 3 vreg output of the i nternal 8 v r egulator. the control circuits are powered from this voltage . p lace a 1 f , x7r or x5r c eramic capacitor between this pin and gnd . 4 gnd analog g round . return of internal control circuit. 5, 6, 7, 14 sw switch node o utput. connect to the output inductor. 8, 9, 10, 11, 12, 13 pgnd power g round. return of low - side power mosfet. 15 bst supply r ail for the high - side g ate d rive. p lace a 0.1 f , x7r or x5r capacitor between sw and bst . 16,17,18,19 pvin power input. connect to the input power source and connect a bypass capacitor between this pin and pgnd. 20 en precision enable p in. an e xternal resistor divider can be used to set the turn - on threshold. to enable the part automatically , connect the en pin to the pvin pin . 21 pgood power - g ood output (open drain). a pull - up resistor of 10 k? to 100 k? is recommended. 22 rt frequency setting. connect a resi s tor between rt and gnd to program the switching fre quency from 2 0 0 khz to 1.4 m hz . 23 sync synchronization i nput. connect this pin to an external clock to synchronize the switching frequency from 200 khz and 1.4 mhz . s ee the oscillator section and synchro nization section for more information . 24 ss soft start c ontrol. connect a capacitor from ss to gnd to program the soft start time. if this pin is open, the regulator uses the internal soft start time. 25 ep, gnd the exposed gnd pad must be soldered to a large, external, copper gnd plane to reduce thermal resistance. 26 ep, sw the exposed sw pad must be connecte d to the sw pins of the adp2384 , using short, wide traces, or else soldered to a large , external , c opper sw plane to reduce thermal resistance.
data sheet adp2384 rev. 0 | page 7 of 24 typical performance characteristics t a = 25 c, v in = 12 v, v out = 3.3 v, l = 3.3 h, c out = 47 f 2 , f sw = 600 khz, unless otherwise noted . 100 50 55 60 65 70 75 80 85 90 95 0 4.0 efficiency (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-3r3m 1.0 2.0 3.5 2.5 1.5 0.5 3.0 10725-004 figure 4 . efficiency at v in = 12 v, f s w = 600 khz 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-3r3m 10725-005 figure 5 . efficiency at v in = 18 v, f sw = 600 khz 20 8 12 18 14 10 6 16 100 50 60 70 80 90 4 shutdown current (a) input voltage (v) t j = ?40c t j = +25c t j = +125c 10725-006 figure 6 . shutdown current vs. v in 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v inductor: fdve1040-6r8m 10725-007 figure 7 . efficiency at v in = 12 v, f sw = 300 khz 4.0 1.0 2.0 3.5 2.5 1.5 0.5 3.0 100 50 55 60 65 70 75 80 85 90 95 0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor: fdve1040-1r5m 10725-008 figure 8 . efficiency at v in = 5 v, f sw = 600 khz 20 8 12 18 14 10 6 16 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 4 quiescent current (ma) input voltage (v) t j = ?40c t j = +25c t j = +125c 10725-009 figure 9 . quiescent current vs. v in
adp2384 data sheet rev. 0 | page 8 of 24 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?40 ?20 0 20 40 60 80 100 120 pvin uvlo threshold (v) temper a ture (c) rising f alling 10725-010 figure 10 . uvlo threshold vs. temperature 3.30 2.90 ?40 120 ss pull-up current (a) temperature (c) 2.95 3.00 3.05 3.10 3.15 3.20 3.25 ?20 0 20 40 60 80 100 10725-0 1 1 figure 11 . ss pin p ul l - u p curren t vs. temperature 630 620 610 570 580 590 600 ?40 120 frequency (khz) temperature (c) ?20 0 20 40 60 80 100 r t = 100k? 10725-012 figure 12 . frequency vs. temperature 0.95 1.25 ?40 ?20 0 20 40 60 80 100 120 en threshold (v) temper a ture (c) 1.05 1.00 1.10 1.15 1.20 rising f alling 10725-013 figure 13 . en threshold vs. temperature 606 604 602 594 596 598 600 ?40 120 feedback voltage (mv) temperature (c) ?20 0 20 40 60 80 100 10725-014 figure 14 . fb voltage vs. temperature 8.4 7.7 ?40 120 vreg voltage (v) temperature (c) 7.8 7.9 8.0 8.1 8.2 8.3 ?20 0 20 40 60 80 100 10725-015 figure 15 . vreg voltage vs. temperature
data sheet adp2384 rev. 0 | page 9 of 24 65 55 15 25 35 45 5 ?40 120 mosfet resistor (m?) temperature (c) ?20 0 20 40 60 80 100 high-side r dson low-side r dson 10725-016 figure 16 . mosfet r dson vs. temperature ch1 10mv ch2 10.0v m2.00 s a ch2 5.00v 1 4 2 t 50.00% b w ch4 2.00 a ? 10725-017 v out (ac) i l sw figure 17 . working mode waveform ch1 2.00v ch2 5.00v m2.00 ms a ch2 3.90v 4 1 2 3 t 50.20% b w ch3 10.0v ch4 2.00 a ? 10725-018 en v out pgood i l figure 18 . voltage pre charged output 7.0 6.5 6.0 4.0 4.5 5.0 5.5 ?40 120 peak current limit threshold (a) temperature (c) ?20 0 20 40 60 80 100 10725-019 figure 19 . current - limit threshold vs. temperature m2.00 ms a ch3 8.60v 4 1 2 3 t 27.00% 10725-020 ? ch1 2.00v ch2 5.00v b w ch3 10.0v ch4 5.00a en v out pgood i out figure 20 . soft start with full load ch2 5.00v ch4 10.0v m1.00 s a ch2 3.40v 4 2 t 50.00% 10725-021 sync sw figure 21 . external synchronization
adp2384 data sheet rev. 0 | page 10 of 24 ch1 100mv m200 s a ch4 2.52 a 1 4 t 70.40% b w ch4 2.00 a ? 10725-022 v out (ac) i out figure 22 . load transient respons e, 1 a to 4 a ch1 2.00v ch2 10.0v m4.00 ms a ch1 1.48v 4 1 2 t 30.40% b w ch4 5.00 a ? 10725-023 v out sw i l figure 23 . output short entry 5 0 1 2 3 4 45 55 65 75 85 95 105 load current (a) ambient temperature (c) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 10725-024 figure 24 . output current vs. ambient temperature at v in = 12 v, f sw = 600 khz ch1 20.0mv ch2 10.0v m1.00 ms a ch3 12.0v 1 2 3 t 30.00% ch3 5.00v i l v out (ac) v in sw 10725-025 b w b w b w figure 25 . line transient response, v in fro m 8 v to 14 v, i out = 4 a ch2 10.0v ch4 5.00 a ? ch1 2.00v b w m4.00ms a ch1 1.72v 4 1 2 t 78.80% 10725-026 v out sw i l figure 26 . output short recovery 5 0 1 2 3 4 45 55 65 75 85 95 105 load current (a) ambient temperature (c) v out = 1v v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 10725-027 figure 27 . output current vs. ambient temperature at v in = 12 v, f sw = 3 00 khz
data sheet adp2384 rev. 0 | page 11 of 24 functional block dia gram + ? + 0.6v i ss ss fb comp amp control logic and mosfet driver with anticross protection bst sw v i_max hiccup mode nfet nfet v i_neg vreg pgnd 0.7v 0.54v ovp pvin vreg uvlo en en_buf slope ramp clk ? + neg current cmp + ? + ? 1.17v 4a 1a ocp cmp + ? + ? driver driver boost regulator bias and driver regulator a cs osc clk slope ramp deglitch sync rt pgood gnd 10725-028 figure 28 . functional block diagram
adp2384 data sheet rev. 0 | page 12 of 24 theory of operation the adp2384 is a synchronous step - down, dc - to - dc regulator that uses a current mode architecture with an integrated high - side power switch and a low - side s ynchronous rectifier. the regulator targets high performance applications that require high efficiency and design flexibility. the adp2384 operate s from an input voltage that ranges from 4.5 v to 20 v and regul ate s the output voltage from 0.6 v to 90% of the input voltage . additional features that maximize design flexibility include the following : programmable switching frequency, programmable soft start, external compensation, precision enable, and a power - good output . control scheme the adp2384 uses a fixed frequency, peak current mode pwm control architecture. at the start of each oscillator cycle, the h igh - side n - mosfet is turned on, putting a positive voltage acro ss the inductor. when the inductor current crosses the peak inductor current th reshold , the high - side n - mosfet is turned off and the low - side n - mosfet is turned on . this puts a negative voltage across the inductor, causing the inductor current to decrease. the low - side n - mosfet stays on for the rest of the cycle (see figure 17) . precision enable/shu tdown the en input pin has a precision analog threshold of 1 .17 v (typical) with 100 mv of hysteresis. whe n the enable voltage exceeds 1.17 v, the regulator turns on ; when it falls below 1. 07 v (typical), the regulator turns off. to force the regulator to auto - matically start when input power is applied, connect en to pvin. the precision en pin has an internal pull - down current source (5 a) that provides a default turn - off when the en pin is open . when t he en pin voltage exceeds 1. 17 v (typical ), the adp2384 is enabled and the internal pull - down current source at the en pin decreases to 1 a , w hich allows user s to program the pvin uvlo and hysteresis. internal regulator ( vreg) the on - board regulator provides a stable supply for the internal circuits. it is recommended that a 1 f ceramic capacitor be placed between the vreg pin and gnd. the inte rnal regulator includes a current - limit circuit to protect the output if the maximum external load current is exceeded. bootstrap circuitry the adp2384 includes a regulator to provide the gate drive voltage for the high - side n - mosfet. it uses differential sensing to generate a 5 v bootstrap voltage between the bst and sw pins . it is recommended that a 0.1 f, x7r or x5r ceramic capacitor be placed between the bst pin and the sw pin. oscillator t he adp2384 switching frequency is controlled by the rt pin. a resistor from rt to gnd can program the switching frequency according to the following equation: f sw (khz) = 15 ) (k 120 , 69 + ? t r a 100 k resistor sets the freque ncy to 600 khz, and a 42.2 k resistor sets the frequency to 1.2 m hz . figure 29 shows the typical relationship between f sw and r t . 1400 20 60 100 140 180 220 260 300 r t (k 1200 1000 800 600 400 200 0 freuenc y (khz) 10725-029 figure 29 . switching frequency vs. r t synchronization t o synchro nize the adp2384 , connect an external clock t o the sync pin. the frequency of the external clock can be in the range of 200 k hz to 1.4 mhz. during synchronization , the regulator operat es in continuous conduction mode ( c cm ) , and the rising edge of the switching waveform runs 180 out of phase to the rising edge of the external clock . when the adp2384 operates in synchroniza tion mode , a resistor must be connected from the rt pin to gnd to program the internal oscillator to run at 90% to 110% of the external synchronization clock.
data sheet adp2384 rev. 0 | page 13 of 24 soft start the adp2384 has integrated soft start circuitry to limit the output voltage rising time and red uce inrush current at startup. t he internal soft start time is calculated using the following equation: t ss_int = (ms) (khz) 1600 sw f a slow er soft start tim e can be programmed by using the ss pin. when a capacitor is connected between the ss pin and g nd, a n internal current charge s the capacitor to establish the soft start ramp. the soft start time is calculated using the following equation: t ss_ext = up ss ss i c _ v 6 . 0 w here: c ss is the soft start capacitance . i ss_up is the soft start pull - up cu rrent (3 .2 a) . the internal error amplifier includes three positive inputs: the internal reference vol tage, the internal digital soft start voltage , and the ss pin voltage. the error amplifier regulates the fb voltage to the lowest of the three voltages. i f the output voltage is charged prior to turn - on, the adp2384 prevents reverse inductor current that would discharge the output capacitor . this function remains active until the soft start voltage exceed s the v oltage on the fb pin. power good the power - good pin (pgood) is an active high, open - drain output that requires an external resistor to pull it up to a voltage . a logic high on the pgood pin indicates that the voltage on the fb pin ( and, therefore, the outp ut voltage) is within regulation. the power - good circuitry monitors the output voltage on the fb pin and compares it to the rising and falling thresholds that are specified in table 1 . if the rising output voltage exceeds the targ et value , the pgood pin is held low. the pgood pin continues to be held low until the falling output voltage returns to the target value. if the output voltage fall s below the target output voltage, the pgood pin is held low. the pgood pin continues to be held low until the rising output voltage returns to the target value. the power - good rising and falling thresholds are shown in figure 30 . there is a 1024 - cycle waiting period before the pgood pin is pulled from low to high , and t here is a 16 - cycle waiting period before the pgood pin is pulled from high to low. 100% 116.7% 105% 90 % 95 % v out (%) pgood v out rising v out falling 1024 cycle deglitch 16 cycle deglitch 1024 cycle deglitch 16 cycle deglitch 10725-130 figure 30 . pgood rising and falling thresholds pea k current - limit and short - circuit protection t he adp 2384 has a peak current - limit protection circuit to prevent current runaway . during the initial soft start, the adp2384 us es frequency foldback to prevent output current runaway. the switching frequency is redu ced according to the voltage on the fb pin , which allows more time for the inductor to discharge. the correlation between the switching frequency and the fb pin voltage is shown in table 5 . table 5. fb p in voltage and switching frequency fb pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v f sw /2 v fb < 0.2 v f sw /4 for protection against heavy loads, t he adp2384 us es a h iccup mo de for overcurrent protection. w hen the inductor peak current reaches the current - limit value, the high - side mosfet turn s off and the low - side mosfet turn s on until the next cycle . the over - current counter increments during this process . i f the overcurrent counter reaches 10 or the fb pin voltage falls to 0. 4 v after the soft start , the regulator enters hiccup mode. the high - side and low - side mosfet s are both turned off. the regulator remains in hiccup mode for 4096 clock cycles a nd then attempts to restart . if th e current - limit fault has cleared, the regulator resumes normal operation. otherwise, it reenters hiccup mode. the adp2384 also provides a sink current limit to prevent the low - side mosfet from sinking a lot of current from the load . when the voltage across the low - side mosfet exceeds the sink current - limit threshold, which is typical ly 20 mv, the low - side mosfet turns off immediately for the rest of th e cycle. both high - side and low - side mosfets turn off until the next clock cycle. in some cases, the input voltage ( v pvin ) ramp rate is too slow or the output capacitor is too large for the output to reach regulation during the soft start process , which causes the regulator to enter the hiccup mode. to avoid such occurrence s, use a resistor divider at the en pin to pro gram the input voltage uvlo, or use a longer soft start time.
adp2384 data sheet rev. 0 | page 14 of 24 over v oltage protection (o vp) the adp2384 includes an ov ervoltage protection feature to protect the regulator against an output short to a higher volta ge supply or when a strong load disconnect transient occurs. if the feedback voltage increases to 0.7 v, t h e i n ternal high - side and low - side mosfet s are turned off until the voltage at the fb p in decreases to 0.63 v . a t that time , the adp2384 resumes normal operation. under v oltage lockout (uvlo ) undervoltage lockout circuitry is integrated in the adp2384 to prevent the occurrence of power - on glitches. if the v pvin voltage fall s below 3.8 v typical, the part shuts down and both the power switch and synchronous rectifier turn off. when the v pvin voltage rises abo ve 4.3 v ty pical, the soft start period is initi ated and the part is enabled. thermal shutdown if the adp2384 junction temperatures rises above 150 c , the internal thermal shutdown circuit turns off the regulator for self - protection. extreme junction tempera tures can be the result of high current operation, poor circuit board thermal design, and/o r high ambient temperature. a 2 5 c hysteresis is included in the thermal shut down circuit so that , if an over temperature event occurs, the adp2384 does not return to normal operation until the on - chip temperature fall s below 12 5 c. upon recovery, a soft start is initiated before normal operation begins .
data sheet adp2384 rev. 0 | page 15 of 24 applications information input capacitor sele ction the input capaci tor reduces the input voltage ripple caused by the switch current on pvin. place the input capacitor as close as possible to the pvin pin. a ceramic capacitor in the 10 f to 47 f r ange is recommended. the loop that is composed of this i nput capacitor, th e high - side n - mosfet, and the low - side n - mosfet must be kept as small as possible. the voltage rating of the input capacitor must be greater than the maximum input voltage. the rms current rating of the input capacitor should be larger than the value calcu lated from the following equation: i c in _ rms = i o ut ) 1 ( d d ? output voltage setti ng the output voltage of the adp2384 is set by an external resistive divider. the resistor values are calculated u sing v out = 0.6 ? ? ? ? ? ? ? ? + bot top r r 1 to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot < 30 k?. table 6 list s the recommended resistor divider v alues for various output voltage s. table 6. resistor divider values for various output voltage s v out (v) r top 1 % ( k? ) r bot 1 % ( k? ) 1.0 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 47.5 15 3.3 10 2.21 5.0 22 3 voltage co nversion limitations the minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. the minimum on time of the adp2384 is typically 12 5 ns. the minimum output voltage for a given input voltage and switching frequency can be calculated using the following equation : v out_min = v in t min_on f sw ? ( r dson_hs ? r dson_ls ) i out_min t min_on f sw ? ( r dson_ls + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson_hs is the high - side mosfet on resistance. r dson_ls is the low - side mosfet on resistance. i out_min is the minimum output current. r l is the series resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maxim um duty cycle. the minimum off time is typically 200 ns, and the maximum duty cycle of the adp2384 is typically 90%. the maximum output voltage , limited by the minimum off time at a given input voltage and freq uency , can be calculated using the following equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson_hs ? r dson_ls ) i out_max (1 ? t min_off f sw ) ? ( r dson_ls + r l ) i out_max (2) where: v out_max is the maximum output voltage. t min_off is the minimum o ff time. i out_max is the maximum output current. the maximum output voltage , limited by the maximum duty cycle at a given input voltage , can be calculated by using the following equation: v out_max = d max v in (3) where d max is the maximum duty cycle . as s how n in equation 1 to equation 3 , reducing the switching frequency alleviates the minimum on time and minimum off time limitation. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and inductor r ipple current. using a small inductor value leads to a faster transient response but degrades efficiency, due to a larger inductor ripple current; using a large inductor value leads to smaller ripple current and better effi ciency but results in a slower tr ansient response. as a guideline, the inductor ripple current, i l , is typically set to one - third of the maximum load curre nt. the inductor value is calcu lated using the following equation: l = sw l out in f i d v v ? ? ) ( where: v in is the input voltage. v out is the output volt age. d is the duty cycle ( d = v out / v in ). i l is the inductor current ripple. f sw is the switching frequency. the adp2384 uses adaptive sl ope compensation in the current l oop to prevent sub harmonic oscillations w hen the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value.
adp2384 data sheet rev. 0 | page 16 of 24 for a duty cycle that is larger than 50%, the minimum inductor value is determined using the following e quation: l (minimum) = sw out f d v ? 2 ) 1 ( the peak induc tor current is calculated by i peak = i o ut + 2 l i ? the saturation current of the inductor must be larger than the peak inductor current. for ferrite core inductors with a quick saturation characteristic, the saturation cu rrent rating of the inductor should be higher than the current - limit threshold of the switch. this prevents the inductor from reaching saturation. the rms current of the inductor is calculated as follows : i rms = 12 2 2 l out i i ? + shielded ferrite cor e materials are recommended for low core loss and low emi. table 7 lists some recommended inductors. output capacitor sel ection the output capacitor selection affects the output ripple voltage load step transient a nd the loop stability of the regulator. for example , during a load step transient where the load is suddenly increased, the output capacitor supplies the load until the control loop can ra mp up the inductor current. the delay caused by the control loop cau ses output undershoot. the output capacitance that is required to satisfy the voltage droop requirement can be calculated u sing the following equation: c out_uv = uv out out in step uv v v v l i k _ 2 ) ( 2 ? ? ? where: k uv is a factor, with a typical setting of k uv = 2. i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example occurs when a load is suddenly removed from the output , and the energy stored in the inductor rushes into the output capacitor, causing the output to overs hoot. the output capacitance that is required to meet the overshoot requirement can be calculated using the following equation: c out_o v = 2 2 _ 2 ) ( out ov out out step ov v v v l i k ? ? + ? where: v out_ov is the allowable overshoot on the output voltage. k ov is a factor, with a typ ical setting of k ov = 2. the output ripple is determi ned by the esr and the value of the capacitance. use the following equation to select a capacitor that can meet the output ri pple requirements: c out_ripple = ripple out sw l v f i _ 8 ? ? r esr = l ripple out i v ? ? _ where: v out_ripple is the allowable output ripple voltage. r esr is the equivalent series resista nce of the output capacitor in o hms (?). table 7 . recommended inductors vendor part no. value (h) i sat (a) i rms (a) dcr (m?) toko fdve1040 - 1r5m 1.5 13.7 14.6 4.6 fdve1040 - 2r2m 2.2 11.4 11.6 6.8 fdve1040 - 3r3m 3.3 9.8 9.0 10.1 fdve1040 - 4r7m 4.7 8.2 8.0 13.8 fdve1040 - 6r8m 6.8 7.1 7.1 20.2 fdve1040 - 100m 10 6.1 5.2 34.1 vishay ihlp4040dz - 1r0m - 01 1.0 36 17.5 4.1 ihlp4040dz - 1r5m - 01 1.5 27.5 15 5.8 ihlp4040dz - 2r2m - 01 2.2 25.6 12 9 ihlp4040dz - 3r3m - 01 3.3 18.6 10 14.4 ihlp4040dz - 4r7m - 01 4.7 17 9.5 16.5 ihlp4040dz - 6r8m - 01 6.8 13.5 8.0 23.3 ihlp4040dz - 100m - 01 10 12 6.8 36.5 wurth elektronik 744325 120 1.2 25 20 1.8 744325 180 1.8 1 8 16 3.5 744325 240 2.4 17 14 4.75 744325 330 3.3 15 12 5.9 744325 420 4.2 14 11 7.1 744325 550 5.5 12 10 10.3
data sheet adp2384 rev . 0 | page 17 of 24 select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple performan ce. the selected output capacitor voltage rating should be greater than the output voltage. the rms current rating of the output capacitor must be larger than the value that is calculated by i c out _ rms = 12 l i ? programming the input voltag e uvlo the adp2384 has a precision enable input that can be used to program the uvlo threshold of the input voltage (see figure 31) . en en cmp adp2384 1.17v 4a 1a pvin r top_en r bot_en 10725-030 figure 3 1 . programming th e input v oltage uvlo use the following equation to calculate r top_en and r bot_en : r top_en = a 1 v 17 . 1 a 5 v 07 . 1 v 17 . 1 v 07 . 1 _ _ ? ? falling in rising in v v r bot_en = v 17 . 1 a 5 v 17 . 1 _ _ _ ? ? en top rising in en top r v r where: v in_rising is the v in rising threshold. v in_falling is the v in falling threshold. compensation des ign for peak current mode control, the power stage can be simplified as a voltage controlled current source supplying current to the output capacitor and load resistor. it is composed of one domain pole and a zero that is contributed by the output capacito r esr. the control - to - output transfer function is based on the following : g vd (s ) = () () out comp vs vs = a vi r 1 2 1 2 z p s f s f ?? + ?? ?? ?? + ?? ?? f z = out esr c r 2 1 f p = out esr c r r + ) ( 2 1 where: a vi = 8.7 a/v. r is the load resistance. c out i s the output capacitance. r esr is the equivalent series resistance of the output capacitor. the adp2384 uses a transconductance amplifier for the error amplifier and to compensate the system. figure 32 sho ws the simplified, peak current mode control, small signal circuit. r esr r + g m r c c cp c out c c r top r bot + a vi v out v comp v out 10725-031 figure 32 . simplified peak current mode c ontrol , small signal c ircuit the compensation components, r c and c c , contribute a zero , and r c and t he optional c cp contribute an optional pole. the closed - loop transfer equation is as follows: t v ( s ) = + ? + cp c m top bot bot c c g r r r ) ( 1 1 s g s c c c c r s s c r vd cp c cp c c c c ? ? ? ? ? ? ? ? + + + the following design guideline shows how to select the r c , c c , and c cp compensation components for cerami c output capacitor applications: 1. determine the cross frequency, f c . generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following equation: r c = vi m c out out a g f c v v 6 . 0 2 3. place the compensation zero at the domain pole , f p ; then determine c c by using the following equation: c c = c out esr r c r r + ) ( 4. c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. c cp = c out esr r c r adi sim p ower design tool the a dp2384 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs that are optimized for a specific design goal. the tools enable the user to generate a full schematic and bill of materials a nd calculate performance in minutes. adisimpower can optimize designs for c ost, area, efficiency, and part count, while taking into consideration the operating conditions and limitations of the ic and all real external components. for more information abou t theadisimpower design tools, refer to www.analog.com/adisimpower . the tool set is available from this website, and users can request an unpopulated board.
adp2384 data sheet rev. 0 | page 18 of 24 design example adp2384 bst fb comp pgood gnd vreg rt sync ss sw pgnd en pvin v in = 12v c ss 22nf c in 10f 25v c out1 47f 6.3v c out2 47f 6.3v c vreg 1f l1 3.3h c bst 0.1f v out = 3.3v r top 10k? 1% r bot 2.21k? 1% c cp 3.9pf c c 1500pf r c 31.6k? 10725-032 r t 100k? figure 33 . schematic for design e xample this section describes the procedures for selecting the external components , based on the example specifications that are listed in table 8 . see figure 33 for the sche matic of this design example. table 8 . step - down dc -to - dc regulator requirements parameter specification input voltage v in = 12.0 v 10% output voltage v out = 3.3 v output current i out = 4 a output voltage ripple ? v out_ripple = 33 mv load transient 5%, 1 a to 4 a, 2 a/s switching frequency f sw = 600 khz output voltage setti ng choose a 10 k? resistor as the top feedback resistor (r top ) , and calculate the bottom feedback resistor (r bot ) by using the following eq uation: r bot = r top ? ? ? ? ? ? ? ? ? to set the output voltage to 3.3 v, the resistors values are as follows: r top = 10 k?, and r bot = 2.21 k? . freuency setting connect a 100 k? resistor from the rt pin to gnd to se t the switching frequency to 60 0 khz . inductor selection the peak - to - peak inductor ripple current, ?i l , is set to 30% of the maximum output current. use the following equation to estimate the inductor value: l = sw l out in f i d v v ? ? where: v in = 12 v . v out = 3.3 v . d = 0.275 . ?i l = 1 .2 a . f s w = 600 khz . this calculation results in l = 3.323 h. choose the standard inductor value of 3.3 h. the peak - to - peak inductor ripple current can be calculated using the following equation: i l = sw out in f l d v v ? this calculation results in ?i l = 1.2 1 a. use the following equation to calculate t he peak induc tor current : i peak = i out + 2 l i ? this calculation results in i peak = 4.605 a. use the following equation to calculate t he rms current flowing through t he inductor : i rms = 12 2 2 l out i i ? + this calculation results in i rms = 4.015 a. based on th e calculated current value, select an inductor with a minimum rms current rating of 4.02 a and a minimum saturation current rating of 4.61 a. however, to protect the inductor from reaching its sat uration point under the current - limit condition, the inductor should be rated for at least a 6 a saturation current for reliable operation. based on the requirements described previously , select a 3.3 h induct or, such as the fdve1040 - 3r3 m from toko , which has a 10.1 m? dcr and a 9.8 a saturation current.
data sheet adp2384 rev . 0 | page 19 of 24 output capacitor sel ection the output capacitor is required to meet both the output voltage ripple and load transient response requirement s. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capacitance value of the output capacitor: c out_ripple = ripple out s l v f i _ 8 ? ? r esr = l ripple out i v ? ? _ this calculation results in c out_ripple = 7.6 f, and r esr = 27 m?. to meet the 5% overshoot and undershoot transient requirements, use the following equations to calculate the capacitance: c out_ov = 2 2 _ 2 ) ( out ov out out step ov v v v l i k ? ? + ? c out_u v = uv out out in step uv v v v l i k _ 2 ) ( 2 ? ? ? where: k ov = k uv = 2 are the coefficients for estimation purpose s. ? i step = 3 a is the load transient step. ? v out_ov = 5%v out is the overshoot voltage. ? v out_uv = 5%v out is the undershoot voltage. this calculation results in c out_ov = 53.2 f, and c out_uv = 20.7 f. according to the calculation, t he output capacitance must be greater than 5 3 f, and the esr of the output capacitor must be smaller than 27 m?. it is recommended that two pieces of 47 f/x5r/6.3 v ceramic capacitor s be used, such as the grm32er60j476me20 from murata, with an esr of 2 m ?. compensation compone nts for better load transient and stability performance, set the cross frequency, f c , to f sw /10. in this case, f sw is running at 600 khz; therefore, the f c is set to 60 khz. the 47 f c eramic output capacitor has a derated value of 3 2 f. r c = a/v 7 . 8 s 470 v 6 . 0 khz 60 f 32 2 v 3 . 3 2 = 3 2 .5 k? c c = ? ? + ? k 5 . 32 f 32 2 ) 002 . 0 825 . 0 ( = 1 629 pf c c p = ? ? k 5 . 32 f 32 2 002 . 0 = 3.9 pf cho ose standard components, as follows: r c = 31.6 k?, c c = 1500 p f, and c cp = 3.9 p f. figure 34 shows the bode plot at 4 a . the cross frequency is 59 khz , and the phase margin is 55 . 60 48 36 24 12 0 60 48 36 24 12 180 144 108 72 36 0 180 144 108 72 36 1k 10k 100k 1m magnitude (db) phase (degrees) freeuency (hz) 10725-040 figure 34 . bode plot at 4 a soft start time prog ram the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating out put volt age overshoot during soft start and limiting the inrush current. set the soft start time to 4 ms. c ss = v 6 . 0 a 2 . 3 ms 4 6 . 0 _ _ = up ss ext ss i t = 2 1.3 nf choose a standard component value , as follows: c ss = 22 n f. input capacitor sele ction a minimum 10 f ceramic capacitor must be placed near the pvin pin. in this application, it is recommended that one 10 f, x5r, 25 v ceramic capacitor be used .
adp2384 data sheet rev. 0 | page 20 of 24 recommended external components table 9 . recommended external components for typical applicat ions with 4 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k?) r bot (k?) r c (k?) c c (pf) c cp (pf) 300 12 1 2.2 680 10 15 47 33 00 150 12 1.2 3.3 680 10 10 59 3300 100 12 1.5 3.3 470 15 10 47 3300 100 12 1.8 4.7 470 20 10 60.4 3300 68 12 2.5 4.7 2 100 47.5 15 22 3300 10 12 3.3 6.8 2 100 10 2.21 29.4 3300 8.2 12 5 10 100 + 47 22 3 34 3300 4.7 5 1 2.2 680 10 15 47 3300 150 5 1.2 2.2 470 10 10 39 3300 100 5 1.5 3.3 470 15 10 47 3300 100 5 1.8 3.3 3 100 20 10 24 3300 15 5 2.5 3.3 2 100 47.5 15 22 3300 10 5 3.3 3.3 2 100 10 2.21 29.4 3300 8.2 600 12 1.5 2.2 3 100 15 10 39 1500 10 12 1.8 2.2 2 100 20 10 31.6 15 00 8.2 12 2.5 2.2 2 47 47.5 15 24 1500 4.7 12 3.3 3.3 2 47 10 2.21 31.6 1500 4.7 12 5 4.7 100 22 3 44.2 1500 2.2 5 1 1 3 100 10 15 26.7 1500 10 5 1.2 1 2 100 10 10 21 1500 10 5 1.5 1.5 2 100 15 10 26.7 1500 10 5 1.8 1.5 100 + 47 20 10 24 1500 8.2 5 2.5 1.5 100 47.5 15 22 1500 4.7 5 3.3 1.5 100 10 2.21 28 1500 4.7 1000 12 2.5 1.5 100 47.5 15 37.4 1000 3.3 12 3.3 2.2 100 10 2.21 47 1000 2.2 12 5 2.2 100 22 3 69 1000 1 5 1 1 3 100 10 15 43.2 1000 8.2 5 1.2 1 2 100 10 10 33 1000 6.8 5 1.5 1 100 + 47 15 10 33 1000 4.7 5 1.8 1 2 47 20 10 30 1000 4.7 5 2.5 1 100 47.5 15 37.4 1000 3.3 5 3.3 1 100 10 2.21 47 1000 2.2 1 680 f: 4 v, sanyo 4tpf680m ; 470 f: 6.3 v, sanyo 6tp f 470m ; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me 20.
data sheet adp2384 rev . 0 | page 21 of 24 circuit board layout recommendations good printed circuit board (pcb) layout is essential for obtaining the best performance from the adp2384 . po or pcb layout can degrade the output regulation , as well as the electromagnetic interference (emi) and electromagnetic compatibility (emc) performance. figure 36 shows an example of a good pcb layout for the adp2384 . for optimum layout, refer to the following guidelines: ? use separate analog ground planes and power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to anal og ground. in addition, connect the ground reference of power components, such as input and output capacitors, to power ground. connect both ground planes to the exposed gnd pad of the adp2384 . ? place the input c apacitor, inductor, and output capacitor as close as possible to the ic , and use short traces. ? ensure that the high current loop traces are as short and as wide as possible. make the high current path from the input capacitor through the inductor, the outp ut capacitor, and the power ground plane back to the input capacitor as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. ? in addition, ensure that the high current path from the power gro und plane through the inductor and output capacitor back to the power ground plane is as short as possible by tying the pgnd pins of the adp2384 to the pgnd plane as close as possible to the input and output cap acitors. ? connect the exposed gnd pad of the adp2384 to a large , external copper ground plane to maximize its power dissipation capability and minimize junction temperature. in addition, connect the e xposed sw p ad to the sw pins of the adp2384 using short, wide traces; or connect the exposed sw pad to a large copper plane of the switching node for high current flow. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. m inimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. to further reduce noise pickup, place an analog ground plane on either side of the fb trace and ensure that the trace is as short as possible to reduce the parasitic capacitance pickup. adp2384 bst fb comp pgood gnd rt sync vreg ss sw pgnd en pvin v in c vreg c in c out r t l c bst v out r top r bot c ss c c r c 10725-033 figure 35 . high current path in the pcb ci rcuit sw sw power ground plane pvin vout output capacitor input bulk cap input bypass cap inductor sw gnd vreg c vreg c bst fb comp pgnd gnd sw sw bst pvin pvin pvin pgnd pgnd pgnd pgnd pgnd sw en pvin r top pgood rt sync ss c ss c c c cp r t r c r bot pull up + via bottom layer trace analog ground plane copper plane 10725-034 figure 36 . recommended pcb layout
adp2384 data sheet rev. 0 | page 22 of 24 typical application s circuit s adp2384 bst fb comp pgood gnd vreg rt sync ss sw pgnd en pvin v in = 12v c in 10f 25v c out1 100f 6.3v c out2 100f 6.3v c out3 100f 6.3v l1 1.5h c bst 0.1f v out = 1.2v r top 10k? 1% r bot 10k? 1% c cp 10pf c c 2.2nf r c 27.4k? 10725-036 c vreg 1f r t 124k? c ss 22nf figure 37 . typical a pplication s c ircuit, v in = 12 v, v out = 1.2 v, i out = 4 a, f s w = 5 00 khz adp2384 bst fb comp pgood gnd vreg rt sync ss sw pgnd en pvin v in = 12v c in 10f 25v c out1 100f 6.3v c out2 100f 6.3v l1 2.2h c bst 0.1f v out = 1.8v r top 20k? 1% r bot 10k? 1% c cp 8.2pf c c 1.5nf r c 31.6k? 10725-035 c vreg 1f r t 100k? figure 38 . typical a pplication s c ircuit using internal soft s tart, v in = 12 v, v out = 1.8 v, i out = 4 a, f sw = 600 khz adp2384 bst fb comp pgood gnd vreg rt sync ss sw pgnd en pvin v in = 12v c in 10f 25v c out 100f 6.3v c ss 22nf c vreg 1f l1 4.7h c bst 0.1f v out = 5v r top 22k? 1% r bot 3k? 1% c cp 2.2pf c c 1.5nf r c 44.2k? r t 124k? 10725-037 figure 39 . typical a pplication s c ircuit with programming switching f requency at 5 00 khz, v in = 12 v, v out = 5 v, i out = 4 a, f sw = 5 00 khz
data sheet adp2384 rev . 0 | page 23 of 24 outline dimensions 0.5 0 bsc 0.5 0 0.40 0.3 0 0.25 0.2 0 0.15 com plian t t o jedec standards mo-220-wg gd . b o t t o m v i e w t o p v i e w pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plan e 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 pin 1 indic a t or 1 2 4 7 12 13 18 19 6 for pro per connection of the expos ed pad, refe r to the pin configuration and fun cti on descriptions secti on of this data sh eet . 2.8 0 2.70 2.60 1.05 0.95 0.85 0.45 0.3 5 0.25 1.50 1.40 1.30 06-24-2010-a e x p o s e d p a d e x p o s e d p a d figure 40 . 24 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 24 - 12) dimensions shown in millimeters ordering guide model 1 temperature range packa ge description package option pack ing adp2384 a cpz n -r 7 ? 40 c to +125 c 24- lead lfcsp_wq cp -24-12 7 tape and reel adp2384 - evalz evaluation board 1 z = rohs compliant part.
adp2384 data sheet rev. 0 | page 24 of 24 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10725 - 0 - 8/12(0)

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